Bitdefender Hypervisor Memory Introspection
icache.h
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1 /*
2  * Copyright (c) 2020 Bitdefender
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 #ifndef _ICACHE_H_
6 #define _ICACHE_H_
7 
8 #include "introtypes.h"
9 #include "bddisasm.h"
10 
11 
19 typedef struct _INS_CACHE_INV_ENTRY
20 {
25  void *WriteHook;
26  void *SwapHook;
28  BOOLEAN Spill;
31 
32 
36 typedef struct _INS_CACHE_ENTRY
37 {
38  INSTRUX Instruction;
48 
49 
53 typedef struct _INS_CACHE_LINE
54 {
57 
58 
62 typedef struct _INS_CACHE
63 {
67 
76  BYTE _Reserved1[2];
80 
81 
86 #define IC_ANY_VAS 0
87 
88 
89 //
90 // API
91 //
94  _In_ PINS_CACHE Cache,
95  _Out_ PINSTRUX Instrux,
96  _In_ QWORD Gva,
97  _In_ QWORD Cr3
98  );
99 
100 INTSTATUS
101 IntIcFlush(
102  _In_ PINS_CACHE Cache
103  );
104 
105 INTSTATUS
107  _In_ PINS_CACHE Cache,
108  _In_ QWORD Gva,
109  _In_ QWORD Cr3
110  );
111 
112 INTSTATUS
114  _In_ PINS_CACHE Cache,
115  _In_ QWORD Gva,
116  _In_ QWORD Cr3,
118  );
119 
120 INTSTATUS
122  _In_ PINS_CACHE Cache,
123  _In_ QWORD Gpa
124  );
125 
126 INTSTATUS
128  _In_ PINS_CACHE Cache,
129  _In_ QWORD Cr3
130  );
131 
132 INTSTATUS
134  _In_ PINS_CACHE Cache,
135  _In_ PINSTRUX Instruction,
136  _In_ QWORD Gva,
137  _In_ QWORD Cr3,
138  _In_ BOOLEAN Global
139  );
140 
141 INTSTATUS
143  _Inout_ INS_CACHE **Cache,
144  _In_ DWORD LinesCount,
145  _In_ DWORD EntriesCount,
146  _In_ DWORD InvCount
147  );
148 
149 INTSTATUS
151  _Inout_ PINS_CACHE *Cache
152  );
153 
154 void
156  void
157  );
158 
159 #endif // _ICACHE_H_
BOOLEAN Spill
True if there is an instruction inside this entry that spills inside the next page.
Definition: icache.h:29
void IntIcDumpIcache(void)
Dumps the entire contents of the implicit, per guest, instruction cache.
Definition: icache.c:55
#define _Out_
Definition: intro_sal.h:22
_Bool BOOLEAN
Definition: intro_types.h:58
struct _INS_CACHE_ENTRY * PINS_CACHE_ENTRY
BOOLEAN Pinned
True if the entry is pinned (it cannot be evicted).
Definition: icache.h:45
DWORD FillRate
How many entries or occupied by valid instructions.
Definition: icache.h:70
DWORD EntriesCount
Number of entries inside each line.
Definition: icache.h:65
uint8_t BYTE
Definition: intro_types.h:47
INTSTATUS IntIcLookupInstruction(PINS_CACHE Cache, PINSTRUX Instrux, QWORD Gva, QWORD Cr3)
Lookup an instruction inside the cache.
Definition: icache.c:495
#define _In_
Definition: intro_sal.h:21
INSTRUX Instruction
The decoded instruction.
Definition: icache.h:38
INTSTATUS IntIcFlushGvaPage(PINS_CACHE Cache, QWORD Gva, QWORD Cr3, BOOLEAN Spill)
Flush all entries cached from a given guest virtual page.
Definition: icache.c:664
struct _INS_CACHE INS_CACHE
QWORD Cr3
Virtual address space containing the instruction. Can be IC_ANY_VAS.
Definition: icache.h:40
struct _INS_CACHE_LINE * PINS_CACHE_LINE
DWORD FlushCount
Number of times the cache has been flushed.
Definition: icache.h:71
int INTSTATUS
The status data type.
Definition: introstatus.h:24
QWORD Gva
The guest virtual page described by this entry.
Definition: icache.h:22
LIST_ENTRY Link
List entry element.
Definition: icache.h:21
DWORD RefCount
Number of times this instruction has been hit.
Definition: icache.h:41
INTSTATUS IntIcCreate(INS_CACHE **Cache, DWORD LinesCount, DWORD EntriesCount, DWORD InvCount)
Create anew instruction cache.
Definition: icache.c:1086
INTSTATUS IntIcFlushGpaPage(PINS_CACHE Cache, QWORD Gpa)
Flush all entries cached from a given guest physical page.
Definition: icache.c:734
DWORD MissCount
Number of cache misses.
Definition: icache.h:69
BOOLEAN Valid
True if the entry is valid.
Definition: icache.h:44
struct _INS_CACHE_INV_ENTRY * PINS_CACHE_INV_ENTRY
INS_CACHE_INV_ENTRY * Invd2
Invalidation entry for the instructions that cross the page boundary.
Definition: icache.h:43
INS_CACHE_INV_ENTRY * Invd1
Invalidation entry for the page containing the instruction.
Definition: icache.h:42
#define _Inout_
Definition: intro_sal.h:20
struct _INS_CACHE_INV_ENTRY INS_CACHE_INV_ENTRY
DWORD PageFlushCount
Number of page flushes.
Definition: icache.h:73
unsigned long long QWORD
Definition: intro_types.h:53
INS_CACHE_ENTRY * Entries
Array containing the entries.
Definition: icache.h:55
void * SwapHook
Swap handle.
Definition: icache.h:26
LIST_HEAD * InsInvGva
Array of invalidation entries.
Definition: icache.h:78
INTSTATUS IntIcDestroy(PINS_CACHE *Cache)
Destroy an instruction cache.
Definition: icache.c:1211
INTSTATUS IntIcFlushAddress(PINS_CACHE Cache, QWORD Gva, QWORD Cr3)
Flush entries cached from a given address.
Definition: icache.c:597
struct _INS_CACHE_LINE INS_CACHE_LINE
BOOLEAN Disabled
True if the cache has been deactivated.
Definition: icache.h:75
QWORD Gpa
The guest physical page described by this entry.
Definition: icache.h:23
uint32_t DWORD
Definition: intro_types.h:49
DWORD LinesCount
Number of lines inside the cache. Must be a power of 2.
Definition: icache.h:64
DWORD InvCount
Number of lines inside the invalidation array. Must be a power of 2.
Definition: icache.h:66
void * WriteHook
EPT write hook handle.
Definition: icache.h:25
INTSTATUS IntIcAddInstruction(PINS_CACHE Cache, PINSTRUX Instruction, QWORD Gva, QWORD Cr3, BOOLEAN Global)
Adds an instruction to the cache.
Definition: icache.c:952
BOOLEAN Dirty
True if the ache was modified after the last flush.
Definition: icache.h:74
INTSTATUS IntIcFlush(PINS_CACHE Cache)
Flush the entire instruction cache.
Definition: icache.c:537
INTSTATUS IntIcFlushVaSpace(PINS_CACHE Cache, QWORD Cr3)
Flush an entire virtual address space.
Definition: icache.c:797
QWORD Gva
The instruction guest virtual address.
Definition: icache.h:39
INS_CACHE_LINE * Lines
Array of cache lines.
Definition: icache.h:77
DWORD HitCount
Number of cache hits.
Definition: icache.h:68
DWORD ReplaceCount
Number of times entries were evicted & replaced by other ones.
Definition: icache.h:72
BOOLEAN Global
True if the entry is global (shared in multiple processes).
Definition: icache.h:46
struct _INS_CACHE * PINS_CACHE
QWORD Cr3
Virtual address space the page belongs to.
Definition: icache.h:24
struct _INS_CACHE_ENTRY INS_CACHE_ENTRY